Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries) typically contain an abrasive material in a liquid carrier and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. Polishing compositions are typically used in conjunction with polishing pads (e.g., a polishing cloth or disk). Instead of, or in addition to, being suspended in the polishing composition, the abrasive material may be incorporated into the polishing pad.
The shallow trench isolation (STI) process is a method for isolating elements of a semiconductor device. In a STI process, a polysilicon layer is formed on a silicon substrate, shallow trenches are formed via etching or photolithography, and a dielectric layer (e.g., an oxide) is deposited to fill the trenches. Due to variation in the depth of trenches, or lines, formed in this manner, it is typically necessary to deposit an excess of dielectric material on top of the substrate to ensure complete filling of all trenches.
The excess dielectric material is then typically removed by a chemical-mechanical planarization process to expose the polysilicon layer. When the polysilicon layer is exposed, the largest area of the substrate exposed to the chemical-mechanical polishing composition comprises polysilicon, which must then be polished to achieve a highly planar and uniform surface. Thus, the polysilicon layer has served as a stopping layer during the chemical-mechanical planarization process, as the overall polishing rate decreases upon exposure of the polysilicon layer.
The STI substrate is typically polished using a conventional polishing composition. However, polishing STI substrates with conventional polishing compositions has been observed to result in over polishing of the substrate surface or the formation of recesses in the STI features and other topographical defects such as microscratches on the substrate surface. Over polishing of the substrate may also result in oxide loss and exposure of the underlying oxide to damage from polishing or chemical activity, which detrimentally affects device quality and performance.
A need remains for polishing compositions and polishing methods that will exhibit desirable planarization efficiency, uniformity, and removal rate during the polishing and planarization of substrates such as semiconductors, especially polysilicon substrates, while minimizing defectivity, such as surface imperfections and damage to underlying structures and topography during polishing and planarization. The invention provides such a polishing composition and method. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.